Stack access control for memory device

ABSTRACT

An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

BACKGROUND

High data reliability, high speed of memory access, lower powerconsumption and reduced chip size are features that are demanded fromsemiconductor memory. In recent years, three-dimensional (3D) memorydevices have been introduced. Some 3D memory devices are formed bystacking dies vertically and interconnecting the dies usingthrough-silicon (or through-substrate) vias (TSVs). Benefits of the 3Dmemory devices include shorter interconnects which reduce circuit delaysand power consumption, a large number of vertical vias between layerswhich allow wide bandwidth buses between functional blocks in differentlayers, and a considerably smaller footprint. Thus, the 3D memorydevices contribute to higher memory access speed, lower powerconsumption and chip size reduction. Example 3D memory devices includeHybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).

For example, High Bandwidth Memory (HBM) is a type of memory including ahigh-performance random access memory (DRAM) interface and verticallystacked DRAMs, FIG. 1A is a schematic diagram of a conventional HBMstack 11 including semiconductor chips, such as an I/F die (e. g. logicdie) 12 and a plurality of core dies (DRAM dies) 13. The HBM stack 11may have two 128-bit channels per core die for a total of eightinput/output channels and a width of 1024 bits in total. For example,each core die of the plurality of the core dies 13 is coupled to twochannels. In this example, the core dies 13 a, 13 b, 13 c and 13 d arecoupled to channels A and C, channels B and D, channels E and G, andchannels F and H, respectively. For example, a clock frequency, acommand sequence, and data can be independently provided for eachchannel. FIG. 1B is a schematic diagram of a conventional HBM stack 21including the I/F die 22 and the plurality of core dies 23. The HBMstack 21 may have two 128-bit channels per core die for a total of eightinput/output channels and a width of 1024 bits in total. For example,each core die of the plurality of the core dies 23 may include twochannels. In this example, a stack group 24 a having a stack identifier(SID) “0” includes the core dies 23 a, 23 b, 23 c and 23 d includingchannels A and C, channels B and D, channels E and G, and channels F andH, respectively. A stack group 24 b having a stack ID (SID) “1” includesthe core dies 23 e, 23 f, 23 g and 23 h including channels A and C,channels B and D, channels E and G, and channels F and H, respectively.Thus, a destination die among a plurality of core dies in each channel(e.g., core dies 23 a and 23 e of channel A) addressed in a command maybe identified by the SID.

FIG. 2A is a wiring diagram of the conventional HBM stack 11 includingthe I/F die 12

and the plurality of core dies 13. The I/F die 12 of the HBM 11 stackprovides interfaces 18 a, 18 b, 18 e and 18 f which provide signals onfour input/output channels among the eight input/output channels, whichfunction independently of each other. Memory arrays of the channel A,channel B, channel E and channel F of the core dies 13 a, 13 b, 13 c and13 d may be coupled to the I/F die 12 via native input/output lines(IOs) 17 a, 17 b, 17 e and 17 f, respectively. For example, the nativeIOs 17 a to 17 f may be implemented as conductive vias. For example, theconductive vias may have a spiral structure. Each core die 13 mayinclude a command circuit for each channel. For example, the core dies13 a to 13 d may include command circuits 16 a to 16 d for channel A,channel B, channel E and channel F, respectively. Thus, clock signals,command signals and data signals for each channel may be transmittedindependently and a plurality of data buses and their respectivechannels can operate individually.

FIG. 2B is a wiring diagram of the conventional HBM stack 21 includingthe I/F die 22 and the plurality of core dies 23. The I/F die 22 of theHBM stack 21 provides interfaces 28 a, 28 b, 28 e and 28 f which providesignals on four input/output channels among the eight input/outputchannels of two stack groups. Memory arrays of channels A, B, E and F ofthe stack group 24 a and memory arrays of channels A, B, E and F of thestack group 24 b may be coupled to the same native input/output lines(IOs) 27 a, 27 b, 27 e and 27 f, respectively. For example, memoryarrays of channel A of the core die 23 a in the stack group 24 a andmemory arrays of channel A of the core die 23 e in the stack group 24 bmay be coupled to the native IO 27 a. Each core die 23 may include acommand circuit for each channel. For example, the core dies 23 a to 23d in the stack group 24 a may include command circuits 26 a to 26 d forchannel A, channel B, channel E and channel F, respectively. The coredies 23 e to 23 h in the stack group 24 b may include command circuits26 e to 26 h for channel A, channel B, channel E and channel F,respectively. Each command circuit 26 may detect the SID in a command,check whether the SID in the command matches with an SID of the stackgroup of the core die 23 including the command circuit 26, and decodethe command. If the SID matches, memory access actions responsive to thecommand may be performed. For example, when the interface 28 a transmitsa command on the input/output line 27 a, the command circuit 26 areceives the command and check whether the SID in the command is “0”.The command circuit 26 a processes the command if the SID is “0” andignores the command if the SID is “1”. The command circuit 26 e alsoreceives the command and check whether the SID in the command is “1”.The command circuit 26 e processes the command if the SID is “1” andignores the command if the SID is “0”. Thus, clock signals, commandsignals and data signals for each channel on each die may be transmittedindependently.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a conventional HBM stack including theI/F die and the plurality of core dies.

FIG. 1B is a schematic diagram of a conventional HBM stacks includingthe I/F die and the plurality of core dies.

FIG. 2A is a wiring diagram of the conventional HBM stack including theI/F die and the plurality of core dies.

FIG. 2B is a wiring diagram of the conventional HBM stacks including theI/F die and the plurality of core dies.

FIG. 3 is a block diagram of an HBM stack in a semiconductor device inaccordance with an embodiment of the present disclosure.

FIG. 4 is a timing diagram of command and data lines on the core dies ofthe HBM stack in accordance with an embodiment of the presentdisclosure.

FIG. 5 is a block diagram of an HBM stack in a semiconductor device inaccordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Various embodiments of the present invention will be explained below indetail with reference to the accompanying drawings. The followingdetailed description refers to the accompanying drawings that show, byway of illustration, specific aspects and embodiments in which thepresent invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice thepresent invention. Other embodiments may be utilized, and structure,logical and electrical changes may be made without departing from thescope of the present invention. The various embodiments disclosed hereinare not necessary mutually exclusive, as some disclosed embodiments canbe combined with one or more other disclosed embodiments to form newembodiments.

FIG. 3 is a block diagram of an HBM stack 30 in a semiconductor devicein accordance with an embodiment of the present disclosure. For example,the HBM stack 30 may include an interface (I/F) die 32 and a pluralityof core dies (DRAM dies) CC0 to CC7. For example, the HBM stack 30 mayinclude a command path, a data strobe path and a data path. In FIG. 3, astack group 34 a includes four core dies (e.g., core chips) CC0 to CC3including CC3 33 d which have an SID “0.” A stack group 34 b includesfour core dies CC4 to CC7 including CC7 33 h which have an SID “1.” TheI/F die 32 may include a command decoder 323 that may receive anintermediate IF command signal IF CMD from a controller (not shown)provided outside of the HBM stack 30, and may provide a plurality ofcommand signals CMD. For example, the plurality of command signals CMDmay include a plurality of row command/address signals R_0[5:0] and aplurality of column command/address signals C_0[7:0] to transmitcommands. In a read operation, the I/F die 32 may also receive a datastrobe signal DQS and data signals DQ[127:0] from the plurality of coredies CC0 to CC7 through a data strobe via 325 and a plurality of datavias 326, respectively. For example, the data strobe via 325 and theplurality of data vias 326 may be through silicon vias (TSV).

For example, the core die CC3 33 d may include a command circuit 333 dand a bypass circuit (e.g., a signal transmission circuit) 37 d. Thecommand circuit 333 d may capture the plurality of command signals CMDincluding a command stack ID (CSID) indicative of a stack group, such asthe stack group 34 a or the stack group 34 b (e.g., the SID being “0” or“1”), associated with a command (e.g., activate, read, write, precharge,etc.) in the plurality of command signals CMD. The bypass circuit 37 dmay include a DSID FIFO circuit 334 d, which may capture the CSIDresponsive to each command and may further provide the captured CSID toa match circuit 336 d. The bypass circuit 37 d may also include a stackidentifier (SID) circuit 335 d. The SID circuit 335 d may store a stackID (SID) “0” of the core die CC3 33 d and provide an inverted signal ofthe stack ID to the match circuit 336 d. For example, the match circuit336 d may be an AND circuit. The match circuit 336 d may receive thecaptured CSID from the DSID FIFO circuit 334 d and the inverted stack IDof the core die CC3 33 d to compare the captured SID in the commandinstructing “read” with the SID “0” indicative of the stack group 34 aand may provide a match signal that is active low (e.g. “0” or a logiclow level for indicating the match). For example, if the CSID in thecommand is indicative of the stack group 34 b and the two SIDs do notmatch, the match circuit 336 d may provide an inactive match signal(e.g., “1” or a logic high level) to a data strobe multiplexer 337 d(e.g., a timing signal selector). The data strobe multiplexer 337 d mayprovide a data strobe signal DQS7 from the core die CC7 33 h as a datastrobe signal DQS through a core data strobe via (TSV) 35 responsive tothe inactive match signal from the match circuit 336 d. If the CSID inthe command is indicative of the stack group 34 a and the two SIDs domatch, the match circuit 336 d may provide an active match signal (e.g.,“0” or a logic low level) to the data strobe multiplexer 337 d, and thedata strobe multiplexer 337 d may provide a data strobe signal DQS3 fromthe core die CC3 33 d as the data strobe signal DQS responsive to theactive match signal from the match circuit 336 d. Thus, either the datastrobe signal DQS7 or the data strobe signal DQS3 may be provided as thedata strobe signal DQS to the data strobe via 325 responsive to the CSIDin the command.

The bypass circuit 37 d may include a data strobe enable circuit 338 d.For example, the data strobe enable circuit 338 d may provide the datastrobe signal DQS7 from the core data strobe via 35 when the matchsignal from the match circuit 336 d is inactive (e.g., “1” or a logichigh level). Thus, the data strobe signal DQS7 may be provided to adouble data rate (DDR) moderator circuit 331 d. For example, the DDRmoderator circuit 331 d may include flip-flops 3310 and 3311. The datastrobe signal DQS7 from the data strobe enable circuit 338 d may enableeither the flip-flop 3310 or the flip-flop 3311. For example, theflip-flop 3310 may latch data signals DT7 from a plurality of core datavias 36 responsive to a positive half period of the data strobe signalDQS7 (e.g., a first half period when the data strobe signal DQS7 is at alogic high level) and the flip-flop 3311 may latch the data signals DT7from the plurality of core data vias 36 responsive to a negative halfperiod of the data strobe signal DQS7 (e.g., a second half period whenthe data strobe signal DQS7 is at a logic low level). In this manner, adouble data rate (DDR) transmission of the data signals DT7 may beexecuted at the timing of the data strobe signal DQS7, when the CSID isindicative of the stack group 34 b. For example, the core data strobevia 35 and the plurality of core data vias 36 may be through siliconvias (TSV).

The bypass circuit 37 d may include a data multiplexer circuit 332 d(e.g., a data signal selector). For example, the data multiplexercircuit 332 d may include a plurality of multiplexers 3320 and 3321provided for data transmissions responsive to the positive half periodand the negative half period of the data strobe signal DQS provided fromthe data strobe multiplexer 337 d respectively. For example, if the CSIDin the command is indicative of the stack group 34 b and the two SIDs donot match, the plurality of multiplexers 3320 and 3321 in the datamultiplexer circuit 332 d may provide the data signals DT7 from the coredie CC7 33 h through the DDR moderator circuit 331 d responsive to theinactive match signal from the match circuit 336 d. If the CSID in thecommand is indicative of the stack group 34 a and the two SIDs do match,the plurality of multiplexers 3320 and 3321 in the data multiplexercircuit 332 d may provide data signals DT3 from the core die CC3 33 dthrough a read FIFO circuit 330 d responsive to the active match signalfrom the match circuit 336 d. For example, the read FIFO circuit 330 dmay be coupled to a memory cell array 350 d to temporarily store dataread out therefrom. The data signals from the plurality of multiplexers3320 and 3321 may be provided to a data moderator 339 d. The datamoderator 339 d may provide the data signals from the plurality ofmultiplexers 3320 and 3321 responsive to the positive half period andthe negative half period of the data strobe signal DQS provided from thedata strobe multiplexer 337 d respectively as data signals DQ[127:0].Thus, either the data signals DT7 or the data signals DT3 may beprovided as the data signals DQ[127:0] to the plurality of data vias 326in a double data rate responsive to the CSID in the command.

For example, the core die CC7 33 h may include a command circuit 333 hand a bypass circuit 337 h. The command circuit 333 h may functionsimilarly to the command circuit 333 d. However, the bypass circuit 37 hmay function differently. For example, an SID circuit 335 h may provideSID “1” and a match circuit 336 h may provide an active match signal(e.g., “0” or a logic low level) constantly irrespective of the outputof the DSID FIFO circuit 334 h. Responsive to the active match signal,the data strobe multiplexer 337 h may provide the data strobe signalDQS7 and the data multiplexer circuit 332 h may provide the data signalsDT7 from the core die CC7 33 h through a read FIFO circuit 330 hresponsive to the constantly active match signal. For example, the readFIFO circuit 330 h may be coupled to a memory cell array 350 h totemporarily store data read out therefrom.

FIG. 4 is a timing diagram of command and data lines on the core dies ofthe HBM stack 30 in accordance with an embodiment of the presentdisclosure. For example, a command (External CMD) “Read” transmitted ina clock cycle (=1tCK) may be received at an interface die (CMD Read@I/F)and forwarded to the core die CC3 33 d. The core die CC3 33 d mayreceive the command at time TO. If the core die CC3 33 d is selected, adata strobe signal DQS3 for the core die CC3 33 d may be activated attime TI, responsive to the command at time TO. Here, the data strobesignal DQS to be provided to the interface die may be based on the datastrobe signal DQS3 from the core die CC3 33 d. On the other hand, if thecore die CC7 33 h is selected, the core die CC3 33 d may forward thecommand to the core die CC7 33 h, The core die CC7 33 h may receive thecommand at time T2. If the core die CC7 33 h is selected, a data strobesignal DQS7 for the core die CC7 33 h may be activated at time T3, whichis later than time T1, responsive to the command at time T2. Here, thedata strobe signal DQS to be provided to the interface die may be basedon the data strobe signal DQS7 from the core die CC7 33 h. Thus, thedata signals may be read using the data strobe signal, either DQS3 orDQS7, that is produced by the same core die that stores and provides thedata signals. Here, the data strobe signal DQS based on the data strobesignal DQS7 (DQS (DQS7 based) @CC3) and a first cycle of data signalsfrom the core die CC7 33 h (FIFO in@CC3) have a time difference lessthan half the clock cycle (tCK), whereas the data strobe signal DQSbased on the data strobe signal DQS3 ((DQS (DQS3 based) @CC3) and thefirst cycle of the data signals from the core die CC7 33 h (FIFO in@CC3)have a time difference longer than half the clock cycle, as shown inFIG. 4. Thus, using the data strobe signal DQS based on the data strobesignal DQS7 (DQS (DQS7 based) @CC3) for reading data from the core dieCC7 33 h (FIFO in@CC3) may provide more accurate read timing than usingthe data strobe signal DQS based on the data strobe signal DQS3 ((DQS(DQS3 based) @CC3), as shown in FIG. 4.

FIG. 5 is a block diagram of an HBM stack 50 in a semiconductor devicein accordance with an embodiment of the present disclosure. For example,the HBM stack 50 may include an interface (I/F) die 52 and a pluralityof core dies CC0 to CC7. For example, the HBM stack 50 may include acommand path, a data strobe path and a data path. In FIG. 5, a stackgroup 54 a includes four core dies (e.g., core chips) CC0 to CC3including CC3 53 d which have an SID “0.” A stack group 54 b includesfour core dies CC4 to CC7 including CC7 53 h which have an SID “1.” TheI/F die 52 may include a command decoder 523 that may receive anintermediate IF command signal IF CMD, and may provide a plurality ofcommand signals CMD. For example, the plurality of command signals CMDmay include a plurality of row command/address signals R_0[5:0] and aplurality of column command/address signals C_0[7:0] to transmitcommands. In a read operation, the I/F die 52 may also receive a datastrobe signal DQS and data signals DQ[127:0] from the plurality of coredies CC0 to CC7 through a data strobe via 525 and a plurality of datavias 526, respectively. For example, the data strobe via 325 and theplurality of data vias 326 may be through silicon vias (TSV).

For example, the core die CC3 53 d may include a command circuit 533 dand a bypass circuit 57 d. The command circuit 533 d may capture theplurality of command signals CMD including a command stack ID (CSID)indicative a stack group, such as the stack group 54 a or the stackgroup 54 b (e.g., the SID being “0” or “1”), associated with a command(e.g., activate, read, write, precharge, etc.) in the plurality ofcommand signals CMD. The bypass circuit 57 d may include a DSID FIFOcircuit 534 d, which may capture the CSID responsive to the command andmay further provide the captured CSID to a match circuit 536 d. Thebypass circuit 57 d may also include a stack ID (SID) circuit 535 d. TheSID circuit 53 5 d may store a stack ID (SID) “0” of the core die CC3 53d and provide an inverted signal of the stack ID to the match circuit536 d. For example, the match circuit 536 d may be an AND circuit. Thematch circuit 536 d may receive the captured CSID from the DSID FIFOcircuit 534 d and the inverted stack ID of the core die CC3 53 d tocompare the captured SID in the command instructing “read” with the SID“0” indicative of the stack group 54 a and may provide a match signalthat is active low (e.g. “0” or a logic low level for indicating thematch). For example, if the CSID in the command is indicative of thestack group 54 b and the two SIDs do not match, the match circuit 536 dmay provide an inactive match signal (e.g., “1” or a logic high level)to a data strobe multiplexer 537 d, and the data strobe multiplexer 537d may provide a data strobe signal DQS7 from the core die CC7 53 h as adata strobe signal DQS through a core data strobe via (TSV) 55responsive to the inactive match signal from the match circuit 536 d. Ifthe CSID in the command is indicative of the stack group 54 a and thetwo SIDs do match, the match circuit 536 d may provide an active matchsignal (e.g., “0” or a logic low level) to the data strobe multiplexer537 d, and the data strobe multiplexer 537 d may provide a data strobesignal DQS3 from the core die CC3 53 d as the data strobe signal DQSresponsive to the active match signal from the match circuit 536 d,Thus, either the data strobe signal DQS7 or the data strobe signal DQS3may be provided as the data strobe signal DQS to the data strobe via 525responsive to the CSID in the command.

The bypass circuit 57 d may include a data strobe enable circuit 538 d.For example, the data strobe enable circuit 538 d may provide the datastrobe signal DQS7 from the core data strobe via 55 when the matchsignal from the match circuit 536 d is inactive (e.g., “1” or a logichigh level). Thus, the data strobe signal DQS7 may be provided to asingle data rate (SDR.) moderator circuit 531 d. For example, the SDRmoderator circuit 531 d may be a flip-flop. The data strobe signal DQS7from the data strobe enable circuit 538 d may enable the SDR moderatorcircuit 531 d. For example, the SDR moderator circuit 531 d may latchdata signals DT7 from a plurality of core data vias 56 responsive to apositive half period of the data strobe signal DQS7 (e.g., a first halfperiod when the data strobe signal DQS7 is at a logic high level). Inthis manner, a single data rate (SDR) transmission of the data signalsDT7 may be executed at the timing of the data strobe signal DQS7, whenthe CSID is indicative of the stack group 54 b. For example, the coredata strobe via 55 and the plurality of core data vias 56 may be throughsilicon vias (TSV),

The bypass circuit 57 d may include a data multiplexer circuit 532 d.For example, the data multiplexer circuit 532 d may be a multiplexerprovided for data transmission responsive to the positive half period ofthe data strobe signal DQS provided from the SDR moderator circuit 531d. For example, if the CSID in the command is indicative of the stackgroup 54 b and the two SIDs do not match, the data multiplexer circuit532 d may provide the data signals DT7 from the core die CC7 53 hthrough the SDR moderator circuit 531 d to a data moderator 539 d,responsive to the inactive match signal from the match circuit 536 d. Ifthe CSID in the command is indicative of the stack group 54 a and thetwo SIDs do match, the data multiplexer circuit 532 d may provide datasignals DT3 from the core die CC3 53 d through a read FIFO circuit 530 dto a data moderator 539 d, responsive to the active match signal fromthe match circuit 536 d. For example, the read FIFO circuit 530 d may becoupled to a memory cell array 550 d to temporarily store data read outtherefrom. The data moderator 539 d may provide the data signals fromthe data multiplexer circuit 532 d responsive to the positive halfperiod of the data strobe signal DQS provided from the data strobemultiplexer 53 7 d respectively as data signals DQ[127:0], Thus, eitherthe data signals DT7 or the data signals DT3 may be provided as the datasignals DQ[127:0] to the plurality of data vias 526 in a single datarate responsive to the CSID in the command.

For example, the core die CC7 53 h may include a command circuit 533 hand a bypass circuit 57 h. The command circuit 533 h may functionsimilarly to the command circuit 533 d. However, the bypass circuit 57 hmay function differently. For example, an SID circuit 535 h may provideSID “1” and a match circuit 536 h may provide an active match signal(e.g., “0” or a logic low level) constantly. Responsive to the activematch signal, the data strobe multiplexer 537 h may provide the datastrobe signal DQS7 and the data multiplexer circuit 532 h may providethe data signals DT7 from the core die CC7 53 h through a read FIFOcircuit 530 h responsive to the constantly active match signal. Forexample, the read FIFO circuit 530 h may be coupled to a memory cellarray 550 h to temporarily store data read out therefrom.

Logic levels of signals and logic gate combinations used in theembodiments described the above are merely examples. However, in otherembodiments, combinations of logic levels of signals and combinations oflogic gates other than those specifically described in the presentdisclosure may be used without departing from the scope of the presentdisclosure.

Although this invention has been disclosed in the context of certainpreferred embodiments and examples, it will be understood by thoseskilled in the art that the inventions extend beyond the specificallydisclosed embodiments to other alternative embodiments and/or uses ofthe inventions and obvious modifications and equivalents thereof. Inaddition, other modifications which are within the scope of thisinvention will be readily apparent to those of skill in the art based onthis disclosure. It is also contemplated that various combination orsub-combination of the specific features and aspects of the embodimentsmay be made and still fall within the scope of the inventions. It shouldbe understood that various features and aspects of the disclosedembodiments can be combined with or substituted for one another in orderto form varying mode of the disclosed invention. Thus, it is intendedthat the scope of at least some of the present invention hereindisclosed should not be limited by the particular disclosed embodimentsdescribed above.

1. An apparatus comprising; a first semiconductor chip; a secondsemiconductor chip; m& a first via and a plurality of second viascoupling the first semiconductor chip and the second semiconductor chip,a first stack group including the first semi conductor chip; and asecond stack group including the second semiconductor chip, wherein thefirst semiconductor chip is configured to provide a first timing signalto the first via and further configured to provide first data to theplurality of second vias responsive to the first timing signal, andwherein the second semiconductor chip is configured to provide the firstdata responsive to the first timing signal when the first semiconductorchip is designated, wherein the second semiconductor chip is furtherconfigured to provide a second timing signal and further configured toprovide second data responsive to the second timing signal when thesecond semiconductor chip is designated, wherein the secondsemiconductor chip comprises: a command circuit configured to receive acommand signal and further configured to provide a command stackidentifier associated with the command signal; and a signal transmissioncircuit configured to receive the first timing signal from the first viaand the first data from the plurality of second vias and furtherconfigured to provide the first data responsive to the first timingsignal, when the command stack identifier is indicative of the firststack group and to provide the second data responsive to the secondtiming signal, when the command stack identifier is indicative of thesecond stack group; and wherein the signal transmission circuitcomprises: a timing signal selector circuit configured to receive thefirst timing signal and the second timing signal and further configuredto provide the first timing signal when the command stack identifier isindicative of the first stack group and to provide the second timingsignal, when the command stack identifier is indicative of the secondstack group; and a data signal selector circuit configured to receivethe first data and the second data, and further configured to providethe first data when the command stack identifier is indicative of thefirst stack group and to provide the second data, when the command stackidentifier is indicative of the second stack group.
 2. (canceled) 3.(canceled)
 4. The apparatus of claim 3, wherein the signal transmissioncircuit further comprises: a stack identifier circuit configured toprovide a chip stack identifier indicative of the second stack group;and a match circuit configured to receive the command stack identifierand the chip stack identifier and further configured to provide a matchsignal responsive to whether the command stack identifier is indicativeof the chip stack identifier.
 5. The apparatus of claim 2, wherein thesignal transmission circuit further comprises a signal data moderatorcircuit configured to provide the first data responsive to the firsttiming signal and the command stack identifier indicative of the firststack group.
 6. The apparatus of claim 5, wherein the firstsemiconductor chip is configured to provide the first data at a doubledata rate, and wherein the signal data moderator circuit is configuredto latch the first data responsive to a first half period and a secondhalf period of the first timing signal.
 7. A semiconductor devicecomprising: a memory array in a stack group associated with a firststack identifier; a command circuit configured to receive a commandsignal, to decode a command and an address on the command signal andfurther configured to provide a command stack identifier associated withthe address; a set of external terminals configured to receive a firstcombination of signals including external data signals and an externaltiming signal; and a signal transmission circuit configured to receivethe first combination of signals from the set of external terminals andfurther configured to receive a second combination of signals includinginternal data signals from the memory array and an internal timingsignal, wherein the signal transmission circuit is configured to providethe first combination of signals if the command stack identifier isdifferent from the first stack identifier and further configured toprovide the second combination of signals if the command stackidentifier is the first stack identifier.
 8. The semiconductor device ofclaim 7, wherein the signal transmission circuit comprises: a timingsignal selector circuit configured to receive the external timing signaland the internal timing signal and further configured to provide eitherthe external timing signal or the internal timing signal as an outputtiming signal, responsive to the command stack identifier, and a datasignal selector circuit configured to receive the external data signalsand the internal data signals and further configured to provide eitherthe external data signals or the internal data signals responsive, atleast in part, to the command stack identifier, wherein the data signalselector circuit is further configured to provide either the externaldata signals or the internal data signals as output data signalsresponsive, at least in part, to the external timing signal or theinternal timing signal, respectively.
 9. The semiconductor device ofclaim 7, wherein the signal transmission circuit further comprises: astack identifier circuit configured to provide the first stackidentifier; and a match circuit configured to receive the command stackidentifier and the first stack identifier and further configured toprovide a match signal responsive to whether the command stackidentifier is indicative of the first stack identifier.
 10. Thesemiconductor device of claim 9, wherein the signal transmission circuitfurther comprises: a timing enable circuit configured to receive theexternal timing signal and the match signal and configured to providethe external timing signal responsive to the match signal; and a signaldata moderator circuit configured to receive the external data signalsfrom a portion of the set of external terminals and to receive theexternal timing signal from the timing enable circuit, and furtherconfigured to provide the external data signals responsive to theexternal timing signal when the command stack identifier indicative ofanother stack group different from the stack group.
 11. Thesemiconductor device of claim 10, wherein the signal data moderatorcircuit comprises at least one flip-flop circuit configured to receivethe external timing signal and at least one external data signal of theexternal data signals and further configured to provide the at least oneexternal data signal responsive to the external timing signal.
 12. Thesemiconductor device of claim 10, wherein the set of external terminalsis configured to provide the first data at a double data rate, andwherein the signal data moderator circuit is configured to latch thefirst data responsive to a first half period and a second half period ofthe first timing signal.
 13. The semiconductor device of claim 12,wherein the signal data moderator circuit comprises at least one pair offlip-flop circuits configured to receive the external timing signal andat least one external data signal of the external data signals, andwherein one flip-flop circuit of the at least one pair of flip-flopcircuits is configured to latch the first data responsive to a firsthalf period and the other flip-flop circuit of the at least one pair offlip-flop circuits is configured to latch the first data responsive to asecond half period of the first timing signal.
 14. The semiconductordevice of claim 12, wherein the signal transmission circuit furthercomprises a data moderator configured to provide the output data signalsresponsive to the positive half period and the negative half period ofthe output timing signal.
 15. A method of transmitting data from a firstsemiconductor chip in a first stack group associated with a first stackidentifier, the method comprising: receiving a command signal; decodinga command on the command signal; providing a command stack identifierassociated with the command; receiving a first combination of signalsincluding external data signals and an external timing signal from asecond semiconductor chip; receiving a second combination of signalsincluding internal data signals from a memory array in the firstsemiconductor chip and an internal timing signal; providing the firstcombination of signals if the command stack identifier is different fromthe first stack identifier; and providing the second combination ofsignals if the command stack identifier is the first stack identifier.16. The method of claim 15, further comprising: receiving the externaltiming signal and the internal timing signal; and providing either theexternal timing signal or the internal timing signal responsive to thecommand stack identifier.
 17. The method of claim 15, furthercomprising: receiving the command stack identifier and the first stackidentifier; and providing a match signal responsive to whether thecommand stack identifier is indicative of the first stack identifier.18. The method of claim 17, further comprising: receiving the externaltiming signal and the match signal; providing the external timing signalresponsive to the match signal; receiving the external data signals andthe external timing signal, and providing the external data signalsresponsive to the external timing signal when the command stackidentifier indicative of another stack group different from the stackgroup.
 19. The method of claim 18, further comprising: latching theexternal data signals responsive to a first half period and a secondhalf period of the external timing signal, wherein the external datasignals are received at a double data rate.
 20. The method of claim 19,wherein the first semiconductor chip comprises at least one pair offlip-flop circuits configured to receive the external timing signal andat least one external data signal of the external data signals, andwherein latching the external data signals comprises: latching theexternal data signals responsive to the first half period of theexternal timing signal by one flip-flop circuit of the at least one pairof flip-flop circuits; and latching the external data signals responsiveto the second half period of the external timing signal by the otherflip-flop circuit of the at least one pair of flip-flop circuits.